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Interconnect planning has been widely regarded as one of the most critical factors in determining the system performance and total power consumption as technology scales. Because of shrinking dimension, on-chip wires are getting more resistive, and the wire delay is becoming larger comparing to gate delay. On the other hand, the self capacitance of wires does not scale with feature size, and as wiring density grows, the total coupling capacitance increases, which results in substantial increment of interconnect power consumption. Two challenges have been posed for on-chip interconnect planning: to quantitatively determine the interconnect impacts upon system performance and power consumption in early design stage, to find novel interconnect strategies that can bridge the gap between gates and wires as technology scales.
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