Robust Two-Phase RZ Asynchronous SoC Interconnects

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Executive Summary

A novel two-phase RZ delay-insensitive asynchronous handshaking protocol for on-chip communication has been developed along with an efficient and robust dual-rail circuit implementation (Transmitter/Receiver). Performance was verified using SPICE simulations with a 0.13?m, 1.2 V technologies and compared to that of the best-in-class asynchronous transceivers in terms of forward and backward latencies, throughput, and energy per bit transfer and design complexity. Results demonstrate the superior overall performance of the new transceiver. Recently, Systems-on-Chip (SoC) designs have grown in complexity to include not only multiple clock domains but also a wide range of blocks (IPs) with various data communication needs and patterns.

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