Row/Column Redundancy to Reduce SRAM Leakage in Presence of Random Within-Die Delay Variation

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Executive Summary

With every new technology node, the share of leakage in total power consumption of cache and other SRAM-based memories increases considerably since dynamic power decreases and leakage increases with technology scaling. Among major leakage components, subthreshold leakage is dominant in cache and other SRAM-based memories in nanometer technologies but gate leakage also effectively increases at very thin gate-oxides. Traditionally, spare rows/columns have been used in two ways: either to replace too leaky cells to reduce leakage, or to substitute faulty cells to improve yield.

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