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Hardware transactional memory is a promising synchronization technology for chip-multiprocessors. It simplifies programming of concurrent applications and allows for higher concurrency than lock based synchronization. Standard transactional memory is optimized for average case throughput, but for real-time systems the authors are interested in worst-case execution times. They propose Real-Time Transactional Memory (RTTM) as a time-predictable synchronization solution for chip-multiprocessors in real-time systems. They define the hardware for time-predictable transactions and provide a bound for the maximum transaction retries. The proposed RTTM is evaluated with a simulation of a Java chip-multiprocessor.
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