Hardware

Sampling-Based Approaches to Accelerate Network-on-Chip Simulation

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Executive Summary

Architectural complexity continues to grow as the authors consider the large design space of multiple cores, cache architectures, Network-on-Chip (NoC) and memory controllers. Simulators are growing in complexity to reflect these system components. However, many full-system simulators fail to utilize the underlying hardware resources such as multiple cores; consequently, simulation times have grown significantly. Long turnaround times limit the range and depth of design space exploration. Communication has emerged as a first class design consideration and has led to significant research into NoCs.

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