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Commonly-used memory units enable a processor to load and store multiple registers in one instruction. The authors showed in 2003 how to extend gcc with a Stack-Location-Allocation (SLA) phase that reduces memory traffic by rearranging the stack and replacing some load/store instructions with load/store-multiple instructions. While speeding up the target code, the technique leaves room for improvement because of the phase ordering of register allocation before SLA. In this paper the authors present SARA which combines SLA and register allocation into a single phase. SARA creates a synergy among register assignment, spill-code generation, and SLA that makes the combined phase generate faster code than a sequence of the individual phases.
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