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This paper studies realization of relaxed memory consistency models in the network-on-chip based Distributed Shared Memory (DSM) multi-core systems. Within DSM systems, memory consistency is a critical issue since it affects not only the performance but also the correctness of programs. The authors investigate the scalability of the relaxed consistency models (weak, release consistency) implemented by using transaction counters. The experimental results compare the average and maximum code, synchronization and data latencies of the two consistency models for various network sizes with regular mesh topologies. The observed latencies rise for both the consistency models as the network size grows. However, the scaling behaviors are different.
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