Download now Free registration required
In Multicore Network-on-Chip, it is preferable to realize Distributed but Shared Memory (DSM) in order to reuse the huge amount of legacy code. Within DSM systems, memory consistency is a critical issue since it affects not only performance but also the correctness of programs. In this paper, the authors investigate the scalability of the weak consistency model, which may be implemented using the concept of a transaction counter. Their experimental results compare synchronization latencies for various network sizes, topologies and lock positions in the network. Average synchronization latency rises exponentially for mesh and torus topologies as the network size grows. However, torus limits the synchronization latency in comparison to mesh.
- Format: PDF
- Size: 273.1 KB