Hardware

Scalable Multi-Core Model Checking Fairness Enhanced Systems

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Executive Summary

Rapid development in hardware industry has brought the prevalence of multi-core systems with shared-memory, which enabled the speedup of various tasks by using parallel algorithms. The Linear Temporal Logic (LTL) model checking problem is one of the difficult problems to be parallelized or scaled up to multi-core. In this paper, the authors propose an on-the-fly parallel model checking algorithm based on the Tarjan's Strongly Connected Components (SCC) detection algorithm. The approach can be applied to general LTL model checking or with different fairness assumptions. Further, it is orthogonal to state space reduction techniques like partial order reduction.

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