Processors

Scheduling Parity Checks for Increased Throughput in Early-Termination, Layered Decoding of QC-LDPC Codes on a Stream Processor

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Executive Summary

A stream processor is a power efficient, high level language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism. Many signal processing algorithms for communications are well matched to stream processor architectures, including partially parallel implementations of layered decoding algorithms such as the Turbo Decoding Message Passing (TDMP) algorithm. Communication among clusters of functional units in the stream processor impose a latency cost during both the message passing phase and the parity check phase of the TDMP algorithm with early termination; the inter cluster communications latency is a significant factor in limiting the throughput of the decoder.

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