Security-Aware SoC Test Access Mechanisms
Test access mechanisms are critical components in digital systems. They affect not only production and operational economics, but also system security. The authors propose a security enhancement for System-on-Chip (SoC) test access that addresses the threat posed by untrustworthy cores. The scheme maintains the economy of shared wiring (bus or daisy-chain) while achieving most of the security benefits of star-topology test access wiring. Using the proposed scheme, the tester is able to establish distinct cryptographic session keys with each of the cores, significantly reducing the exposure in cases where one or more of the cores contains malicious or otherwise untrustworthy logic.