Date Added: Jul 2009
One of the most important hurdles of technology scaling is process variations, i.e., variations in device characteristics. Process variations cause large fluctuations in performance and power consumption in the manufactured chips. In addition, these fluctuations cause reductions in the chip yields. In this paper, the authors present an analysis of a representative high-performance processor architecture and show that the caches have the highest probability of causing yield losses under process variations. They then propose a novel selective wordline voltage boosting mechanism that aims at reducing the latency of the cache lines that are affected by process variations.