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During the process of development of any system, system reliability is of utmost importance. Specially when designing a processor, it is desired that a processor function correctly even in the presence of faults. This concept is commonly referred to as fault tolerance. The fault tolerant microprocessor systems used in safety critical applications need to be thoroughly validated during the design stages. As feature size reduces in future, there is an increased probability of transient and intermittent faults. Now these systems on chip integrated circuits contain both digital and analog cores. Test cost for such mixed signal SOC is much higher than the digital SOC that allows the analog and digital cores to be tested.
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