Self-Test Techniques in SoC for Low Power Consumption
A generic built-in self-test needed for SoC devices implementing for low power consumption. In this the authors proposed a new technique to generate a fully pre-computed test set in a deterministic BIST using simple gray counter within a reasonable clock cycles. Conversely, they consider only a small part of the circuit which is to be tested is active and the other parts of the circuit are fed with low leakage input patterns. After that every CUT is fed by a gray counter which makes the overall consumption extremely low. Here, they combine this BIST with the external testing Strategy for low power consumption using slow-testers. That all concurrent operations are performed in less number of clock pulses.