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Hardware masking is a well-known countermeasure against Side-Channel Attacks (SCA). Like many other countermeasures, the side-channel resistance of masked circuits is susceptible to low-level circuit effects. However, no detailed analysis is available that explains how, and to what extent, these low-level circuit effects are causing side-channel leakage. The authors' first contribution is a unified and consistent analysis to explain how glitches and inter-wire capacitance cause side-channel leakage on masked hardware. Their second contribution is to show that inter-wire capacitance and glitches are causing side-channel leakage of comparable magnitude according to HSPICE simulations. Their third contribution is to confirm their analysis with a successful DPA-attack on a 90nm COMS FPGA implementation of a glitch-free masked AES S-Box.
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