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The world's demand for high-speed devices and equipments are growing very drastically. Every individual researcher in all country is marching towards, to achieve it .The role of Design Engineer has become very important to cater the above needs. As per Moor' law packing density doubles every eighteen months. This is possible only by scaling down the device size, so that more number of transistor's can be packed in a small area. Of course this is aimed at, to reduce power loss, delay, chip size, etc. In order to understand the concept behind downscaling, without affecting the device characteristics, it is good to simulate and analyze the result with known standard result that is available.
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