Download now Free registration required
The fast simulation of Chip Multi-Processors (CMPs) presents a critical challenge to the architecture research community as both industry and academia shift their research focus to multi-core design. Parallel simulation is a technique to accelerate micro-architecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, the authors explore the simulation paradigm of simulating each core of a target CMP in one thread and then spreading the threads across the hardware thread contexts of a host CMP. They implement several parallel simulation schemes using POSIX Threads (Pthreads). They start with cycle-by-cycle simulation and then relax the synchronization condition in various schemes, which they call slack simulations.
- Format: PDF
- Size: 223.8 KB