Sneak Path Testing and Fault Modeling for Multi-Level Memristor-Based Memories
Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation, compactness and ability to store multiple bits in a single cell. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, the authors will examine the defect mechanisms in Multi-Level Cells (MLC) using memristors and develop efficient fault models. They will also investigate efficient test techniques for multi-level memristor based memories.