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Soft errors are a growing concern for processor reliability. Recent work has motivated architecture level studies of soft errors since the architecture level can mask many raw errors and architectural solutions can exploit workload knowledge. The author's paper focuses on the modeling and analysis of soft error issues at the architecture level. The authors start with the widely used method for estimating the architecture level Mean Time To Failure (MTTF) due to soft errors. The method first calculates the failure rate for an architecture level component as the product of its raw error rate and an Architecture Vulnerability Factor (AVF).
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