Hardware Investigate

Software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling

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Executive Summary

This paper presents a methodology and a tool-chain to perform estimation and optimization of the energy consumption associated to software execution on tiny embedded systems. The estimation phase is based on an ISA-level characterization of the target processor, while the optimization phase is made combining the estimation process with design space exploration in order to exploit fine-grained dynamic voltage and frequency scaling. The proposed approach operates at compile-time, with the granularity of single C functions and almost automatically augments the source code.

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