Solving FPGA Routing Using Ant Colony Optimization With Minimum CPU Time
In this paper ANT colony optimization algorithm are used to solve geometric FPGA routing for a route based routing constraint model in FPGA design architecture which is a NP complete problem in nature and many conventional and heuristic algorithms have been developed and proposed for this problem. In this paper ant colony optimization algorithm is applied on the Boolean equation consist of the FPGA routing problem. The ACO based solution to SAT is then compared with the other SAT solver algorithms such as zChaff and GRASP. The experimental results suggest that the developed ant colony optimization algorithm has taken less CPU time as compared to zChaff and GRASP to route a FPGA circuit.