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As more computing cores are integrated onto a single chip, the effect of network communication latency is becoming more and more significant on multi-core Network-on-Chips (NoCs). For data-parallel applications, the authors study the model of parallel speedup by including network communication latency in Amdahl's law. The speedup analysis considers the effect of network topology, network size, traffic model and computation/communication ratio. They also study the speedup efficiency. In the multi-core NoC platform, a real data-parallel application, i.e. matrix multiplication, is used to validate the analysis. The theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up.
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