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The accuracy of the prediction results and the applicability of the under laying algorithms are influenced by several parameters. In addition, both issues are interdependent. Thus, the first part of this paper examined this connection regarding memory and cache modeling as well as analysis. In addition, here, the authors learned by experience about the difficulties of modeling more complex bus interfaces (MPC750). The second part introduced a methodology to predict the timing behavior for multi-issue machines. Modern processor architecture is designed to increase the utilization of the parallelism which is inherent to programs. Beside pipelining, data and instruction caching or multi-issue processing, speculative branch processing is an advanced technique (e.g. provided by the MPC750) which is strongly coupled to the behavior of the memory hierarchy.
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