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During routing, memory is required to store both architectural data and temporary routing data. The architectural data is static, and provides a representation of the physical routing resources and programmable connections on the device. The authors show that by taking advantage of the regularity in FPGAs, they can reduce the amount of information that must be explicitly represented, leading to significant memory savings. The temporary routing data is dynamic, and contains scoring parameters and trace-back information for each routing resource in the FPGA. By studying the lifespan of the temporary routing data objects, they develop several memory management schemes to reduce this component.
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