Processors

Static Program Partitioning for Embedded Processors

Free registration required

Executive Summary

Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the paper, the user is required to partition and arrange the code such that appropriate fragments are loaded into the memory at appropriate times. The authors explore automatic partitioning by defining an optimality criterion and provide a lazy algorithm which tries to combine procedures which should be loaded together. The procedures which do not fit into local memory are further partitioned. The lazy nature of the algorithm facilitates using multiple heuristics to identify good partitions.

  • Format: PDF
  • Size: 186.9 KB