Hardware

Static Task Partitioning for Locked Caches in Multi-Core Real-Time Systems

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Executive Summary

Massive multi-core architectures with tens of cores are becoming more prevalent in embedded systems. However, their acceptance in the real-time systems domain is rather low due to challenges in system analysis and predictability. Recent real-time systems research has focused on shared cache architectures. In such systems, tasks across all cores share the same cache (typically at level 2). In contrast, tile-based architectures with massive numbers of cores have private caches, only. At larger numbers of cores, it becomes important to utilize all resources efficiently and share cores among hard, soft and non real-time tasks. In such a scenario, it becomes difficult to analyze cache behavior statically.

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