Static Timing Analysis for Modeling QoS in Networks on Chip

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Executive Summary

Networks-on-Chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC's shared resources, Quality of Service and resource allocation are major concerns for system designers. In particular, a model for the properties of packet delivery through the network is desirable. The authors present a methodology for packet-level static timing analysis in NoCs. Their methodology quickly and accurately gauges the performance parameters of a virtual-channel wormhole NoC without simulation. The network model can handle any topology, link capacities, and buffer sizes. It provides per-flow delay analysis that is orders-of-magnitude faster than simulation while being significantly more accurate than prior static modeling techniques. Using a carefully derived and reduced Markov chain, the model can statically represent dynamic network state.

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