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Very Long Instruction Word- (VLIW-) based processors have become widely adopted as a basic building block in modern Systemon-Chip designs. Advances in clustered VLIW architectures have extended the scalability of the VLIW architecture paradigm to a large number of functional units and very-wide-issue widths. A central challenge with wide-issue clustered VLIW architecture is the availability of programming and automated compiler methods that can fully utilize the available computational resources. Existing compilation approaches for clustered-VLIW architectures are based on extensions of previously developed scheduling algorithms that primarily focus on the maximization of Instruction-Level Parallelism (ILP). However, many applications do not have sufficient ILP to fully utilize a large number of functional units.
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