Study and Performance Evaluation of Xilinx HDLC Controller and FCS Calculator
In this paper, design, simulation and implementation design of HDLC Controller provides a high performance. This design is then coded in a Hardware Description Language (VHDL). The functioning of the coded design is to simulate on simulation software (e.g. ModelSim). After proper simulation, the design is synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated.