Hardware

Study of Modeling for Scalable and Monitorable Network on Chip

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Executive Summary

The performance of multiple processor based on Network on Chip (NoC) is limited to the communication efficiency of network. It is difficult to be optimized of routing and arbitration algorithm and be assessed of performance in the beginning of design because of its complex test cases. This paper constructs a scalable and monitored system level model with System C for NoC with Packet Connected Circuit (PCC) protocol. The overall performance and transfer details can be evaluated particularly by running the model, and the statistical basis can also be provided to the optimization of designing NoC.

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