Sub Pipelined Architecture for Self-Test Techniques of Crypto Devices Based on AES With High Throughput
Testing of the equipment is very essential before being put into service. The testing has to be done by the latest technique. This paper describes a generic built-in self-test strategy for crypto-devices with sub pipelining architecture by implementing symmetric encryption algorithms. Taking advantage of the inner iterative structures of crypto-cores, test facilities are easily set-up for self-test of the crypto-cores, built-in pseudorandom test generation. Main advantages of the proposed test implementation are high throughput and no visible scan chain, this testing provides crypto-cores with 100% fault coverage with a notable speed has been achieved in the range of 3.22Gbps for 128-bit AES algorithm.