Synergic Parallel Compact Finite Automatons for Accelerating Multi-String Matching

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Multi-string matching is a key technique for network security applications like Network Intrusion Detection Systems (NIDS) and anti-virus scanners, where every packet is inspected against tens of thousands of predefined signatures in real-time. Existing DFA-based research have claimed to achieve high processing throughput at an expense of extremely high memory cost, so fail to be used in the embedded systems like high-speed routers where only limited on-chip resources are available. This paper proposes a multi-string matching acceleration scheme named Synergic Parallel Compact Finite Automata (SPC-FA) matching system together with its conflict-free dispatching algorithm and the corresponding memory optimization mechanisms.