SysGen Architecture for Visual Information Hiding Framework

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The development time and cost for DSP solution have been improved significantly due to proliferation of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator (SysGen). The present work explains a method for the design and implementation of a real-time DSP application using SysGen for Matlab. The scheme represents architecture for visual information hiding framework where information bit is embedded into the host image by means of LSB replacement technique. The design is implemented targeting a Spartan-3A DSP edition board (XC3SD3400A-4FGG676C).