Temperature-And Cost-Aware Design of 3D Multiprocessor Architectures
3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates temperature induced problems that affect system reliability, performance, leakage power and cooling cost. In addition, the overhead due to Through-Silicon-Vias (TSVs) and scribe lines contribute to the overall area, affecting wafer utilization and yield. As any of the aforementioned parameters can limit the 3D stacking process of a MultiProcessor SoC (MPSoC), in this paper the authors investigate the tradeoffs between cost and temperature profile across various technology nodes. They study how the manufacturing costs change when the number of layers, defect density, number of cores, and power consumption vary.