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One major obstacle faced by designers when entering the multicore era is how to harness the massive computing power which these cores provide. Since Instructional-Level Parallelism (ILP) is inherently limited, one single thread is not capable of efficiently utilizing the re-source of a single core. Hence, Simultaneous MultiThreading (SMT) micro-architecture can be introduced in an effort to achieve improved system resource utilization and a correspondingly higher instruction through-put through the exploitation of Thread-Level Parallelism (TLP) as well as ILP. However, when multiple threads execute concurrently in a single core, they automatically compete for system resources.
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