Date Added: Oct 2009
This paper provides an introduction to Error Correcting Code (ECC) DRAM. It discusses the risks of a system encountering random memory errors and the approaches for combating them. DRAM is susceptible to random occurrences of bit(s) flipping, or changing logical states unexpectedly. While originally attributed to alpha particles from the device packaging, later research has shown this to largely be the result of background radiation. There are various influences which can vary the frequency of the errors, for example chip design techniques, memory density, etc.