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A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and reduce the delay of interconnects significantly across the dies. However, a major challenge in 3D technology is the increased power density, which gives rise to the concern of heat dissipation within the processor. High temperatures trigger voltage and frequency throttling in hardware, which degrade the chip performance. Moreover, high temperatures impair the processor's reliability and reduce its lifetime. To alleviate this problem, the authors propose in this paper an OS-level scheduling algorithm that performs thermal-aware task scheduling on a 3D chip.
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