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3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both latency and power benefits due to reductions in critical wires. However, 3D stacking of active devices can potentially exacerbate existing thermal problems. In this work, the authors propose a family of Thermal Herding techniques that reduces 3D power density and locates a majority of the power on the top die closest to the heat sink.
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