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Packet classification is a central component of modern network functionality, yet satisfactory memory usage and overall performance remains an elusive challenge at the highest speeds. The recent emergence of chip multiprocessors and other low-cost, highly parallel processing hardware provides a promising platform on which to realize increased classification performance. In this paper the authors analyze the performance of packet classification in the context of parallel, shared-memory architectures. They begin with two classic algorithms - Aggregated Bit Vector and HiCuts - and parallelize each of them multiple ways. They discuss the tradeoffs of different architectures in the context of these algorithms, and they evaluate the schemes on both Chip MultiProcessor (CMP) and Symmetric MultiProcessor (SMP) hardware.
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