Networking

Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors

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Executive Summary

Current design complexity trends, poor wire scalability, and power limitations argue in favor of highly modular on-chip systems. Today's state-of-the-art CMPs already feature up to a hundred discrete cores. With increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized accelerators are anticipated in the near future. Meanwhile, server consolidation and cloud computing paradigms have emerged as profit vehicles for exploiting abundant resources of chip-multiprocessors. As multiple, potentially malevolent, users begin to share virtualized resources of a single chip, CMP-level Quality-of-Service (QOS) support becomes necessary to provide performance isolation, service guarantees, and security

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