Towards Hierarchical Cluster Based Cache Coherence for Large-Scale Network-on-Chip

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Executive Summary

Network-on-Chip (NoC) is considered to be a promising scheme for future MPSoCs. NoC can provide high bandwidth, low latency, parallel communication and scalable design exploration space. The increasing integration density will allow NoCs to integrate more and more components. The memory system will consume large part of on-chip area. The organization of memory system will greatly affect the performance of NoC. There exist plenty of shared data among nodes. Because of the inherent contention in accessing shared recourses, it may incur long communication latencies, which will limit the performance of NoC. Introduction of private caches will be helpful in reducing average latencies. Especially in the NoC context, caches also increase memory effective utilization and reduce communication volume.

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