Tri-Gate Bulk CMOS Technology for Improved SRAM Scalability

Download Now Free registration required

Executive Summary

A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling.

  • Format: PDF
  • Size: 526.6 KB