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Network on Chip (NoC) has established itself as an alternative to the on chip bus to meet the increasing requirements of complex communication needs of System on Chip (SoC). A popular choice of topology for generic Network on Chip has been 2D Meshes. Similarly for application specific Network on Chip irregular topologies customized to application needs is preferred. However as the feature size continue to shrink and integration densities continue to increase, the interconnect delay is emerging as the critical bottleneck for the performance of 2D NoC. The advances in technology such as over the cell routing and Through-Silicon-Vias (TSV) has made possible performance conscious and scalable Network on Chip with more than 2 dimension.
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