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The problem of scheduling on multi-core systems remains one of the hottest and the most challenging topics in systems research. Introduction of Non-Uniform Memory Access (NUMA) multi-core architectures further complicates this problem, as on NUMA systems the scheduler needs not only consider the placement of threads on cores, but also the placement of memory. Hardware performance counters and hardware-supported instruction sampling, available on major CPU models, can help tackle the scheduling problem as they provide a wide variety of potentially useful information characterizing system behavior.
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