Hardware

Using Multiple Compacted Responses to Diagnose Scan Response Errors During Testing

Date Added: Jan 2011
Format: PDF

Scan test vector and response volume are becoming problematic, and in industrial designs are complicated by the presence of unknown values in test responses. Recent work has addressed this problem by devising X-tolerant codes that allow both compaction of test responses and guaranteed detection of errors despite the presence of unknown response values. The X-MISR scan compaction architecture [Mitra04] shows how random codes can be generated on-chip and used as X-tolerant codes to provide a single testing architecture that can be tuned to the needs of the chip design and the ability to remove unknowns in test responses without change to the architecture itself, yet provides several orders of magnitude of test response compaction.