Hardware

Variability of Multistage Synchronizers

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Executive Summary

System-on-Chip (SoC) designs typically employ multiple clock domains to interface several externally clocked circuits operating at different frequencies, and to reduce power and area by breaking large clock trees into multiple small ones. The principal challenge of such Globally Asynchronous Locally Synchronous (GALS) architectures is the need to reliably communicate between the different clock domains. To achieve high reliability margins in modern process technologies, multistage synchronizers are often used. In this paper, the authors develop analytical formulae to calculate the probability of failure and the number of stages to use in such synchronizers.

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