Storage

Variation-Aware Software Techniques for Cache Leakage Reduction using Value-Dependence of SRAM Leakage due to Within-Die Process Variation

Date Added: Oct 2007
Format: PDF

The authors observe that the same SRAM cell leaks differently, under within die process variations, when storing 0 and 1; this difference can be up to 3 orders of magnitude (averaging 57%) at 60mv variation of threshold Voltage (Vth). Thus, leakage can be reduced if most often the values with less leakage are stored in the cache SRAM cells. They show applicability of this proposal by presenting three binary-optimization and software-level techniques for reducing instruction cache leakage: They reorder instructions within basic-blocks so as to match up the instructions with the less-leaky state of their corresponding cache cells, statically apply register-renaming with the same aim and at boot time, initialize unused cache-lines to their corresponding less-leaky values.