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The main objective of this paper is to present an approach to accomplish verification in the early design phases of a system, which allows one to make the system verification easier, specifically for those systems with timing restrictions. For this purpose the authors' use RT-UML sequence diagrams in the design phase and they translate these diagrams into timed automata for performing the verification by using model checking techniques. Specifically, the paper uses the Object Management Group's UML Profile for Schedulability, Performance, and Time and from the specifications written using this profile the author obtains the corresponding timed automata.
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