VHDL Implementation of High Speed AXI2.0 Protocol with DDR3 Controller
With the need of application, chip with a single processor can't meet the need of more and more complex computational task. The authors are able to integrate multiple processors on a chip thanks to the development of integrated circuit manufacturing technology. This paper proposes the implementation of AXI 2.0 protocol which removes the limitation of communication architecture, which would otherwise reduce the speed of data transfer in System-on-Chip (SoC). They have also implemented DDR3 controller which was then interface with AXI 2.0 protocol. Proposed protocol was synthesized on Xilinx 13.1 and simulated using Modelsim 6.5e.