Processors

Vicis: A Reliable Network for Unreliable Silicon

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Executive Summary

Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wear-out inevitably make margining uneconomical or impossible. The ElastIC project seeks to address this by creating a large-scale chip-multiprocessor that can self-diagnose, adapt, and heal. Creating large, flexible designs in this environment naturally lends itself to the repetitive nature of Network-on-Chip (NoC), but the loss of a single link or router will result in complete network failure. In this paper, the authors present Vicis, an ElastIC-style NoC that can tolerate the loss of many network components due to wear-out induced hard faults.

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